/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/

#ifndef SYS_BASE_REG_H
#define SYS_BASE_REG_H

#ifdef __cplusplus
extern "C" {
#endif

/*=================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
=================================================================================================*/
#include <stdint.h>

/*=================================================================================================
*                              SOURCE FILE VERSION INFORMATION
=================================================================================================*/


/*=================================================================================================
*                                     FILE VERSION CHECKS
=================================================================================================*/

/*=================================================================================================
*                                          CONSTANTS
=================================================================================================*/


/*=================================================================================================
*                                      DEFINES AND MACROS
=================================================================================================*/
/* IO definitions (access restrictions to peripheral registers) */
/**
*   IO Type Qualifiers are used
*   \li to specify the access to peripheral variables.
*   \li for automatic generation of peripheral register debug information.
*/
#ifndef __IO
#ifdef __cplusplus
  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
#else
  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
#endif
#define     __O     volatile             /*!< Defines 'write only' permissions                */
#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
#endif


/*which cpu*/
/*which cpu*/
#define ISR_ATTR_SECURE        0x1
#define ISR_ATTR_SAFETY        0x2
#define ISR_ATTR_REALTM        0x4
#define ISR_ATTR_SWITCH        0x8
#define ISR_ATTR_SOCR5         0x10
/*level or edge( bit 16)*/
#define ISR_ATTR_LEVEL      (0x00000)
#define ISR_ATTR_EDGE       (0x20000)
#define IS_EDGE(a)          ((a & 0x30000) >> 16)

/********new api for R5 Safety**************/
#define CPU0_IDX            (1)
#define CPU1_IDX            (2)

/* Definition for CPU ID */
#define XPAR_CPU_ID         (0U)


#define CPU_TYPE_C1200_SWITCH
#define CPUTYPE_C1200_SW

/*=================================================================================================
*                                              ENUMS
=================================================================================================*/
/**
 * @brief Defines the Interrupt Numbers definitions
 *
 * This enumeration is used to configure the interrupts.
 *
 * Implements : IRQn_Type_Class
 */
typedef enum
{
    /* Auxiliary constants */
    NOTAVAIL_IRQN                   = -128,             /**< NOT AVAILABLE DEVICE SPECIFIC INTERRUPT */

    SW_INTR_R5_0_CTI_INT0                                                  = 32,
    SW_INTR_R5_0_CTI_INT1                                                  ,
    SW_INTR_R5_1_CTI_INT0                                                  ,
    SW_INTR_R5_1_CTI_INT1                                                  ,
    SW_INTR_R5_2_CTI_INT0                                                  ,
    SW_INTR_R5_2_CTI_INT1                                                  ,
    SW_INTR_R5_0_APB_TX_INT0                                               ,
    SW_INTR_R5_0_APB_TX_INT1                                               ,
    SW_INTR_R5_0_APB_TX_INT2                                               ,
    SW_INTR_R5_0_APB_TX_INT3                                               ,
    SW_INTR_R5_1_APB_TX_INT0                                               ,
    SW_INTR_R5_1_APB_TX_INT1                                               ,
    SW_INTR_R5_1_APB_TX_INT2                                               ,
    SW_INTR_R5_1_APB_TX_INT3                                               ,
    SW_INTR_R5_2_APB_TX_INT0                                               ,
    SW_INTR_R5_2_APB_TX_INT1                                               ,
    SW_INTR_R5_2_APB_TX_INT2                                               ,
    SW_INTR_R5_2_APB_TX_INT3                                               ,
    SW_INTR_GMAC_INTR                                                      ,
    SW_INTR_GMAC_PERCH_RX_INTR0                                            ,
    SW_INTR_GMAC_PERCH_RX_INTR1                                            ,
    SW_INTR_GMAC_PERCH_RX_INTR2                                            ,
    SW_INTR_GMAC_PERCH_RX_INTR3                                            ,
    SW_INTR_GMAC_PERCH_TX_INTR0                                            ,
    SW_INTR_GMAC_PERCH_TX_INTR1                                            ,
    SW_INTR_GMAC_PERCH_TX_INTR2                                            ,
    SW_INTR_GMAC_PERCH_TX_INTR3                                            ,
    SW_INTR_PCS_INTR0                                                      ,
    SW_INTR_PCS_INTR1                                                      ,
    SW_INTR_PCS_INTR2                                                      ,
    SW_INTR_PCS_INTR3                                                      ,
    SW_INTR_NPU_INTR0                                                      ,
    SW_INTR_NPU_INTR1                                                      ,
    SW_INTR_NPU_INTR2                                                      ,
    SW_INTR_NPU_INTR3                                                      ,
    SW_INTR_NPU_INTR4                                                      ,
    SW_INTR_NPU_INTR5                                                      ,
    SW_INTR_NPU_INTR6                                                      ,
    SW_INTR_NPU_INTR7                                                      ,
    SW_INTR_NPU_INTR8                                                      ,
    SW_INTR_NPU_INTR9                                                      ,
    SW_INTR_NPU_INTR10                                                     ,
    SW_INTR_NPU_INTR11                                                     ,
    SW_INTR_NPU_INTR12                                                     ,
    SW_INTR_NPU_INTR13                                                     ,
    SW_INTR_NPU_INTR14                                                     ,
    SW_INTR_NPU_INTR15                                                     ,
    SW_INTR_NPU_INTR16                                                     ,
    SW_INTR_NPU_INTR17                                                     ,
    SW_INTR_EPP_XGMAC_SBD_INTR_COMBAND                                     ,
    SW_INTR_FLEXRAY_INTR0                                                  ,
    SW_INTR_FLEXRAY_INTR1                                                  ,
    SW_INTR_LIN_INTR0                                                      ,
    SW_INTR_LIN_INTR1                                                      ,
    SW_INTR_LIN_INTR2                                                      ,
    SW_INTR_LIN_INTR3                                                      ,
    SW_INTR_LIN_INTR4                                                      ,
    SW_INTR_LIN_INTR5                                                      ,
    SW_INTR_CAN_INTR0                                                      ,
    SW_INTR_CAN_INTR1                                                      ,
    SW_INTR_CAN_INTR2                                                      ,
    SW_INTR_CAN_INTR3                                                      ,
    SW_INTR_CAN_INTR4                                                      ,
    SW_INTR_CAN_INTR5                                                      ,
    SW_INTR_CAN_INTR6                                                      ,
    SW_INTR_CAN_INTR7                                                      ,
    SW_INTR_CAN_INTR8                                                      ,
    SW_INTR_CAN_INTR9                                                      ,
    SW_INTR_CAN_INTR10                                                     ,
    SW_INTR_CAN_INTR11                                                     ,
    SW_INTR_CAN_INTR12                                                     ,
    SW_INTR_CAN_INTR13                                                     ,
    SW_INTR_CAN_INTR14                                                     ,
    SW_INTR_CAN_INTR15                                                     ,
    SW_INTR_TIMER_INTR0                                                    ,
    SW_INTR_TIMER_INTR1                                                    ,
    SW_INTR_TIMER_INTR2                                                    ,
    SW_INTR_TIMER_INTR3                                                    ,
    SW_INTR_TIMER_INTR4                                                    ,
    SW_INTR_TIMER_INTR5                                                    ,
    SW_INTR_TIMER_INTR6                                                    ,
    SW_INTR_TIMER_INTR7                                                    ,
    SW_INTR_WDT_INTR0                                                      ,
    SW_INTR_WDT_INTR1                                                      ,
    SW_INTR_WDT_INTR2                                                      ,
    SW_INTR_WDT_INTR3                                                      ,
    SW_INTR_WDT_INTR4                                                      ,
    SW_INTR_WDT_INTR5                                                      ,
    SW_INTR_MSGBOX_INTR0                                                   ,
    SW_INTR_MSGBOX_INTR1                                                   ,
    SW_INTR_MSGBOX_INTR2                                                   ,
    SW_INTR_MSGBOX_INTR3                                                   ,
    SW_INTR_MSGBOX_INTR4                                                   ,
    SW_INTR_MSGBOX_INTR5                                                   ,
    SW_INTR_MSGBOX_INTR6                                                   ,
    SW_INTR_MSGBOX_INTR7                                                   ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR0                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR1                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR2                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR3                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR4                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR5                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR6                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR7                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR8                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR9                                          ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR10                                         ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR11                                         ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR12                                         ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR13                                         ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR14                                         ,
    SW_INTR_SIMPLE_DMA_FUNC_INTR15                                         ,
    SW_INTR_SEC_INTR0                                                      ,
    SW_INTR_SEC_INTR1                                                      ,
    SW_INTR_SEC_INTR2                                                      ,
    SW_INTR_SEIP_HASH_BUSERR_INTR                                          ,
    SW_INTR_SEIP_SKE_BUSERR_INTR                                           ,
    SW_INTR_DMA_INTR0                                                      ,
    SW_INTR_DMA_INTR1                                                      ,
    SW_INTR_DMA_INTR2                                                      ,
    SW_INTR_DMA_INTR3                                                      ,
    SW_INTR_DMA_CMNREG_INTR                                                ,
    SW_INTR_SW_IPC_BANK0                                                   ,
    SW_INTR_SW_IPC_BANK1                                                   ,
    SW_INTR_SW_IPC_EVENT0                                                  ,
    SW_INTR_PLL_INTR0                                                      ,
    SW_INTR_PLL_INTR1                                                      ,
    SW_INTR_CLOCK_MONITOR_ERROR0                                           ,
    SW_INTR_CLOCK_MONITOR_ERROR1                                           ,
    SW_INTR_SWITCH_SYS_CTR_CSR_ADDR_PTY_ERR                                ,
    SW_INTR_SWITCH_SYS_CTR_CSR_W_DATA_PTY_ERR                              ,
    SW_INTR_SWITCH_SYS_CRM_CSR_ADDR_PTY_ERROR                              , 
    SW_INTR_SWITCH_SYS_CRM_CSR_W_DATA_PTY_ERR                              , 
    SW_INTR_R5_0_SAFETY_INTERRUPT                                          , 
    SW_INTR_R5_1_SAFETY_INTERRUPT                                          , 
    SW_INTR_R5_2_SAFETY_INTERRUPT                                          , 
    SW_INTR_NOC_MAINMISSIONINT                                             , 
    SW_INTR_NOC_TIMEOUT_INTR                                               , 
    SW_INTR_NOC_R5_0_PARITY_INTR                                           , 
    SW_INTR_NOC_R5_1_PARITY_INTR                                           , 
    SW_INTR_NOC_R5_2_PARITY_INTR                                           , 
    SW_INTR_NOC_CRIT_PARITY_INTR                                           , 
    SW_INTR_NOC_PERI_PARITY_INTR                                           , 
    SW_INTR_NOC_RAM_PARITY_INTR                                            , 
    SW_INTR_EPP_NOC_CSFTY_INTR                                             , 
    SW_INTR_SRAM0_ECC_DECODE_ERR_INTR                                      , 
    SW_INTR_SRAM1_ECC_DECODE_ERR_INTR                                      , 
    SW_INTR_STANDBY_SRAM_ECC_DECODE_ERR_INTR                               , 
    SW_INTR_SRAM0_ECC_ENCODE_ERR_INTR                                      , 
    SW_INTR_SRAM1_ECC_ENCODE_ERR_INTR                                      , 
    SW_INTR_STANDBY_SRAM_ECC_ENCODE_ERR_INTR                               , 
    SW_INTR_SRAM0_ECC_ERROR_M_INTR                                         , 
    SW_INTR_SRAM1_ECC_ERROR_M_INTR                                         , 
    SW_INTR_STANDBY_SRAM_ECC_ERROR_M_INTR                                  , 
    SW_INTR_SRAM0_ECC_ERROR_S_INTR                                         , 
    SW_INTR_SRAM1_ECC_ERROR_S_INTR                                         , 
    SW_INTR_STANDBY_SRAM_ECC_ERROR_S_INTR                                  , 
    SW_INTR_MSGBOX_SFTY_INTR                                               , 
    SW_INTR_GMAC_SFTY_UE_INTR                                              , 
    SW_INTR_GMAC_SFTY_CE_INTR                                              , 
    SW_INTR_LSP_APB_PARITY_INTR                                            , 
    SW_INTR_CAN_ASILD_SAFETY_INTR0                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR1                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR2                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR3                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR4                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR5                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR6                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR7                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR8                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR9                                         , 
    SW_INTR_CAN_ASILD_SAFETY_INTR10                                        , 
    SW_INTR_CAN_ASILD_SAFETY_INTR11                                        , 
    SW_INTR_CAN_ASILD_SAFETY_INTR12                                        , 
    SW_INTR_CAN_ASILD_SAFETY_INTR13                                        , 
    SW_INTR_CAN_ASILD_SAFETY_INTR14                                        , 
    SW_INTR_CAN_ASILD_SAFETY_INTR15                                        , 
    SW_INTR_CAN_SAFETY_INTR0                                               , 
    SW_INTR_CAN_SAFETY_INTR1                                               , 
    SW_INTR_CAN_SAFETY_INTR2                                               , 
    SW_INTR_CAN_SAFETY_INTR3                                               , 
    SW_INTR_CAN_SAFETY_INTR4                                               , 
    SW_INTR_CAN_SAFETY_INTR5                                               , 
    SW_INTR_CAN_SAFETY_INTR6                                               , 
    SW_INTR_CAN_SAFETY_INTR7                                               , 
    SW_INTR_CAN_SAFETY_INTR8                                               , 
    SW_INTR_CAN_SAFETY_INTR9                                               , 
    SW_INTR_CAN_SAFETY_INTR10                                              , 
    SW_INTR_CAN_SAFETY_INTR11                                              , 
    SW_INTR_CAN_SAFETY_INTR12                                              , 
    SW_INTR_CAN_SAFETY_INTR13                                              , 
    SW_INTR_CAN_SAFETY_INTR14                                              , 
    SW_INTR_CAN_SAFETY_INTR15                                              , 
    SW_INTR_SEC_TRNG_ALARM                                                 , 
    SW_INTR_SDMA0_SAFE_INTR                                                , 
    SW_INTR_EPP_XGMAC_SBD_SFTY_UE_INTR                                     , 
    SW_INTR_DMA_SAFE_INTR                                                  , 
    SW_INTR_EPP_SFTY_UE_INTR0                                              , 
    SW_INTR_EPP_SFTY_UE_INTR1                                              , 
    SW_INTR_EPP_SFTY_UE_INTR2                                              , 
    SW_INTR_EPP_SFTY_CE_INTR                                               , 
    SW_INTR_PCS_SFTY_UE_INTR0                                              , 
    SW_INTR_PCS_SFTY_UE_INTR1                                              , 
    SW_INTR_PCS_SFTY_UE_INTR2                                              , 
    SW_INTR_PCS_SFTY_UE_INTR3                                              , 
    SW_INTR_APB_BUS_PARITY_INTR                                            , 
    SW_INTR_EPP_XGMAC_SBD_SFTY_RE_INTR                                     , 
    SW_INTR_NPU_INTR18                                                     ,
    SW_INTR_SOC2SW_INTR0                                                   ,
    SW_INTR_SOC2SW_INTR1                                                   ,
    SW_INTR_SOC2SW_INTR2                                                   ,
    SW_INTR_SOC2SW_INTR3                                                   ,
    SW_INTR_SOC2SW_INTR4                                                   ,
    SW_INTR_SOC2SW_INTR5                                                   ,
    SW_INTR_SOC2SW_INTR6                                                   ,
    SW_INTR_SOC2SW_INTR7                                                   ,
    SW_INTR_SOC2SW_INTR8                                                   ,
    SW_INTR_SOC2SW_INTR9                                                   ,
    SW_INTR_SOC2SW_INTR10                                                  ,
    SW_INTR_SOC2SW_INTR11                                                  ,
    SW_INTR_SOC2SW_INTR12                                                  ,
    SW_INTR_SOC2SW_INTR13                                                  ,
    SW_INTR_SOC2SW_INTR14                                                  ,
    SW_INTR_SOC2SW_INTR15                                                  ,
    SW_INTR_RT2SW_INTR0                                                    ,
    SW_INTR_RT2SW_INTR1                                                    ,
    SW_INTR_RT2SW_INTR2                                                    ,
    SW_INTR_RT2SW_INTR3                                                    ,
    SW_INTR_RT2SW_INTR4                                                    ,
    SW_INTR_RT2SW_INTR5                                                    ,
    SW_INTR_RT2SW_INTR6                                                    ,
    SW_INTR_RT2SW_INTR7                                                    ,
    SW_INTR_RT2SW_INTR8                                                    ,
    SW_INTR_RT2SW_INTR9                                                    ,
    SW_INTR_RT2SW_INTR10                                                   ,
    SW_INTR_RT2SW_INTR11                                                   ,
    SW_INTR_RT2SW_INTR12                                                   ,
    SW_INTR_RT2SW_INTR13                                                   ,
    SW_INTR_RT2SW_INTR14                                                   ,
    SW_INTR_RT2SW_INTR15                                                   ,
    SW_INTR_SAFETY2SW_INTR0                                                , 
    SW_INTR_SAFETY2SW_INTR1                                                ,
    SW_INTR_SAFETY2SW_INTR2                                                ,
    SW_INTR_SAFETY2SW_INTR3                                                ,
    SW_INTR_SAFETY2SW_INTR4                                                ,
    SW_INTR_SAFETY2SW_INTR5                                                ,
    SW_INTR_SAFETY2SW_INTR6                                                ,
    SW_INTR_SAFETY2SW_INTR7                                                ,
    SW_INTR_SAFETY2SW_INTR8                                                ,
    SW_INTR_SAFETY2SW_INTR9                                                ,
    SW_INTR_SAFETY2SW_INTR10                                               ,
    SW_INTR_SAFETY2SW_INTR11                                               ,
    SW_INTR_SAFETY2SW_INTR12                                               ,
    SW_INTR_SAFETY2SW_INTR13                                               ,
    SW_INTR_SAFETY2SW_INTR14                                               ,
    SW_INTR_SAFETY2SW_INTR15                                               ,
    NUMBER_OF_INT_VECTORS            /**< Number of interrupts in the Vector table */
}IRQn_Type;

/*************************************MEM_TOP_REG************************************/
#define SRAM_BASE_ADDR	          (0x18000000)

/*************************************IPC_TOP_REG************************************/
#define IPC_BASE                  (0x33100000)
#define IPC_A55_SHARE_MEM         (0x8ff00000)
#define IPC_A55_MSG_SIZE          (0x40)

/*************************************UART_TOP_REG***********************************/
#define UART0_BASE_ADDR           (0xD0003000)
#define UART1_BASE_ADDR           (0xD0004000)
#define UART_IP_CNT               (2)

/*******************************************MSGBX_TOP_REG****************************/
#define MSGBOX_01_BASE_ADDR       (0x20120000)
#define MSGBOX_23_BASE_ADDR       (0x20220000)
#define MSGBOX_45_BASE_ADDR       (0x20320000)

/******************************************GIC_TOP_REG*******************************/
#define GIC_BASE_ADDR             (0x21700000)

/*******************************************CAN_TOP_REG******************************/
#define CAN0_BASE_ADDR            (0x21710000)
#define CAN1_BASE_ADDR            (0x21718000)
#define CAN2_BASE_ADDR            (0x21720000)
#define CAN3_BASE_ADDR            (0x21728000)
#define CAN4_BASE_ADDR            (0x21730000)
#define CAN5_BASE_ADDR            (0x21738000)
#define CAN6_BASE_ADDR            (0x21740000)
#define CAN7_BASE_ADDR            (0x21748000)
#define CAN8_BASE_ADDR            (0x21750000)
#define CAN9_BASE_ADDR            (0x21758000)
#define CAN10_BASE_ADDR           (0x21760000)
#define CAN11_BASE_ADDR           (0x21768000)
#define CAN12_BASE_ADDR           (0x21770000)
#define CAN13_BASE_ADDR           (0x21778000)
#define CAN14_BASE_ADDR           (0x21780000)
#define CAN15_BASE_ADDR           (0x21788000)
#define CAN_IP_CNT                (2)

/*******************************************FLEXRAY_TOP_REG**************************/
#define FLEXRAY0_BASE_ADDR        (0x21790000)
#define FLEXRAY1_BASE_ADDR        (0x21792000)
#define FLEXRAY_IP_CNT            (2)

/*******************************************LSP_CRM_REG******************************/
#define LSP0_CRM_BASE_ADDR        (0x217A0000)
#define LSP_BUS_CNT               (1)

/*******************************************LIN_CRM_REG******************************/
#define LIN0_BASE_ADDR            (0x217A1000)
#define LIN1_BASE_ADDR            (0x217A2000)
#define LIN2_BASE_ADDR            (0x217A3000)
#define LIN3_BASE_ADDR            (0x217A4000)
#define LIN4_BASE_ADDR            (0x217A5000)
#define LIN5_BASE_ADDR            (0x217A6000)
#define LIN_IP_CNT                (5)

/*******************************************DMA_REG******************************/
//#define DMA_BASEADDR            (0xC0020000)
#define DMA_BASEADDR            (0x217E0000) //sw DMA

/*******************************************WDT_CRM_REG******************************/
#define WDT0_BASE_ADDR	          (0x217A7000)
#define WDT1_BASE_ADDR	          (0x217A8000)
#define WDT2_BASE_ADDR	          (0x217A9000)
#define WDT3_BASE_ADDR	          (0x217AA000)
#define WDT4_BASE_ADDR	          (0x217AB000)
#define WDT5_BASE_ADDR	          (0x217AC000)
#define WDT_IP_CNT                (6)

/*************************************TIMER_PWM_TOP_REG******************************/
#define TIMER0_PWM0_BASE_ADDR	    (0x217AD000)
#define TIMER_PWM_IP_CNT          (1)

/*************************************TOP_BASE_REG***********************************/
#define TOP_CRM_BASE_ADDR         (0x217B0000)


#define IPC_SEM_BASE_ADDR         (0x30100000)
#define TOP_SYS_CTRL_BASE_ADDR    (0x217B1000)


/*************************************SEC_SAF_CRM_TOP_REG****************************/
#define SAFETY_CRM_ADDR                     (0xC0030000)
#define SEC_SAFETY_RESET_CTRL 	            (0xC0030008)
#define SAFETY_RELEASE_CTRL                 (SAFETY_CRM_ADDR+0x8)
#define SEC_SAFE_SYS_CTRL_PLL_INTR_CFG      (0xC0030040)
#define TOP_CRM_BLOCK_HW_RST1	              (0x330020C0)
#define SYS_CTRL_RVBARADDR0 	              (0x3300002C)
#define SYS_CTRL_R_ECU_ERR_STATE            (0x33000130)

#define SW_SYS_CTRL_ADDR        (0x217B1000)
#define RT_PMM_ADDR             (0xD1035000)
#define SW_CRM_CSR_BASE_ADDR		(0x217B0000U)
#define WR_PROT_OFFSET              (0x00U)
#define TEST0_OFFSET                (0x10U)
#define TEST1_OFFSET                (0x14U)
#define COLD_RST_OFFSET             (0x20U)
#define WARM_RST_OFFSET             (0x24U)
#define SW_RST_OFFSET               (0x28U)
#define ETH_RST_OFFSET              (0x2cU)
#define WDT_RST_MASK_OFFSET         (0x30U)
#define MAIN_PLL_CTRL_OFFSET        (0x40U)
#define MAIN_PLL_DIV_OFFSET         (0x44U)
#define MAIN_PLL_FRC_DIV_OFFSET     (0x48U)
#define MAIN_PLL_SSC_CTRL_OFFSET    (0x4cU)
#define ETH_PLL_CTRL_OFFSET         (0x50U)
#define ETH_PLL_DIV1_OFFSET         (0x54U)
#define ETH_PLL_FRC_DIV_OFFSET      (0x58U)


/********************************************A55 sys ctrl reg****************************************/
#define A55_CTRL_BASE_ADDR                  (0x33000000)
#define A55_CTRL_CPU_BOOT_ADDR              (A55_CTRL_BASE_ADDR + 0x2C)

/******************************************FIREWALL*************************************************/
#define SECURE_SRAM_FIREWALL                (0xF0001000+0x10)

/*************************************LB_LSP0_TOP*********************************************/
#define LB_LSP0_TOP_BASE_ADDR                      (0xC175F000)
#define LSP0_LOCAL_SF_RST_CTRL_REG_ADDR            (LB_LSP0_TOP_BASE_ADDR + 0x0000)
#define LSP0_GLB_CTRL_REG_ADDR                     (LB_LSP0_TOP_BASE_ADDR + 0x0004)
#define LSP0_DIV_CTRL_REG_ADDR                     (LB_LSP0_TOP_BASE_ADDR + 0x0008)
#define LSP0_DIV_CTRL1_REG_ADDR                    (LB_LSP0_TOP_BASE_ADDR + 0x000C)
#define LSP0_DIV_CTRL2_REG_ADDR                    (LB_LSP0_TOP_BASE_ADDR + 0x0010)
#define LSP0_QSPI_CFG_CTRL_REG_ADDR                (LB_LSP0_TOP_BASE_ADDR + 0x0014)
#define LSP0_DEBUG_CTRL_REG_ADDR                   (LB_LSP0_TOP_BASE_ADDR + 0x0018)
#define LSP0_SAFETY_FUN_CTRL_REG_ADDR              (LB_LSP0_TOP_BASE_ADDR + 0x001C)
#define LSP0_SPI_SLAVE_CTRL_REG_ADDR               (LB_LSP0_TOP_BASE_ADDR + 0x0020)

/*************************************LB_LSP0_TOP*********************************************/
#define LB_LSP1_TOP_BASE_ADDR                      (0x20021000)
#define LSP1_LOCAL_SF_RST_CTRL_REG_ADDR            (LB_LSP1_TOP_BASE_ADDR + 0x0000)
#define LSP1_GLB_CTRL_REG_ADDR                     (LB_LSP1_TOP_BASE_ADDR + 0x0004)
#define LSP1_DIV_CTRL_REG_ADDR                     (LB_LSP1_TOP_BASE_ADDR + 0x0008)
#define LSP1_DIV_CTRL1_REG_ADDR                    (LB_LSP1_TOP_BASE_ADDR + 0x000C)
#define LSP1_DIV_CTRL2_REG_ADDR                    (LB_LSP1_TOP_BASE_ADDR + 0x0010)
#define LSP1_QSPI_CFG_CTRL_REG_ADDR                (LB_LSP1_TOP_BASE_ADDR + 0x0014)
#define LSP1_DEBUG_CTRL_REG_ADDR                   (LB_LSP1_TOP_BASE_ADDR + 0x0018)
#define LSP1_SAFETY_FUN_CTRL_REG_ADDR              (LB_LSP1_TOP_BASE_ADDR + 0x001C)
#define LSP1_SPI_SLAVE_CTRL_REG_ADDR               (LB_LSP1_TOP_BASE_ADDR + 0x0020)

/*********************Safety crm reg*********************************************************/


/*************************************GIC_TOP_REG****************************************/
#define SAFETY_GIC_BASE_ADDR            (0x21700000)
#define XPAR_BSTGIC_NUM_INSTANCES       (1U)            /* Definitions for driver SCUGIC */
#define XPAR_PSU_RCPU_GIC_DEVICE_ID     (0U)            /* Definitions for peripheral PSU_RCPU_GIC */
#define XPAR_PSU_RCPU_GIC_BASEADDR      (0x21702000U)
#define XPAR_PSU_RCPU_GIC_HIGHADDR      (0x21701FFFU)
#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR (0x21701000U)

#define CPU_GIC_BASE                    SAFETY_GIC_BASE_ADDR
#define CPU_GIC_DISTRIBUTOR             (CPU_GIC_BASE + 0x1000)
#define CPU_GIC_CPU_INTERCACE           (CPU_GIC_BASE + 0x2000)
#define CPU_GIC_VIR_INTF_CTL            (CPU_GIC_BASE + 0x4000)
#define CPU_GIC_VIR_INTF_CTL_A          (CPU_GIC_BASE + 0x5000)
#define CPU_GIC_VIR_CPU_INTF            (CPU_GIC_BASE + 0x6000)

#define CPU_GIC_GICD_CTLR               *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x000))
#define CPU_GIC_GICD_TYPER              *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x004))
#define CPU_GIC_GICD_IIDR               *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x008))
#define CPU_GIC_GICD_IGROUPR0           *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x080))
#define CPU_GIC_GICD_IGROUPR0_ADDR                             (CPU_GIC_DISTRIBUTOR + 0x080)
#define CPU_GIC_GICD_ISENABLER0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x100))
#define CPU_GIC_GICD_ISENABLER0_ADDR                           (CPU_GIC_DISTRIBUTOR + 0x100)
#define CPU_GIC_GICD_ICENABLER0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x180))
#define CPU_GIC_GICD_ICENABLER0_ADDR                           (CPU_GIC_DISTRIBUTOR + 0x180)
#define CPU_GIC_GICD_ISPENDR0           *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x200))
#define CPU_GIC_GICD_ICPENDR0           *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x280))
#define CPU_GIC_GICD_ISACTIVER0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x300))
#define CPU_GIC_GICD_ICACTIVER0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x380))
#define CPU_GIC_GICD_IPRIORITYR0        *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x400))
#define CPU_GIC_GICD_IPRIORITYR0_ADDR                          (CPU_GIC_DISTRIBUTOR + 0x400)
#define CPU_GIC_GICD_ITARGETSR0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0x800))
#define CPU_GIC_GICD_ITARGETSR0_ADDR                           (CPU_GIC_DISTRIBUTOR + 0x800)

#define CPU_GIC_LEVEL_SENSITIVE         (0 << 0)    /*Interrupt Configruation Registers*/
#define CPU_GIC_EDGE_TRIGGERED          (1 << 0)
#define CPU_GIC_N_N_MODEL               (0 << 1)
#define CPU_GIC_1_N_MODEL               (1 << 1)

#define CPU_GIC_GICD_ICFGR0             *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xC00))
#define CPU_GIC_GICD_ICFGR0_ADDR        (CPU_GIC_DISTRIBUTOR + 0xC00)

#define CPU_GIC_GICD_PPISR              *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xD00))
#define CPU_GIC_GICD_SPISR0             *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xD04))
#define CPU_GIC_GICD_SGIR               *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xF00))
#define CPU_GIC_GICD_SGIR_ADDR           (CPU_GIC_DISTRIBUTOR + 0xF00)
#define CPU_GIC_GICD_CPENDSGIR0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xF10))
#define CPU_GIC_GICD_SPENDSGIR0         *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xF20))
#define CPU_GIC_GICD_PIDR4              *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xFD0))
#define CPU_GIC_GICD_PIDR5              *((volatile uint32_t *)(CPU_GIC_DISTRIBUTOR + 0xFD4))

#define CPU_GIC_GICC_CTLR               *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0000))
#define CPU_GIC_GICC_PMR                *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0004))
#define CPU_GIC_GICC_BPR                *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0008))
#define CPU_GIC_GICC_IAR                *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x000C))
#define CPU_GIC_GICC_EOIR               *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0010))
#define CPU_GIC_GICC_RPR                *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0014))
#define CPU_GIC_GICC_HPPIR              *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0018))
#define CPU_GIC_GICC_ABPR               *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x001C))
#define CPU_GIC_GICC_AIAR               *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0020))
#define CPU_GIC_GICC_AEOIR              *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0024))
#define CPU_GIC_GICC_AHPPIR             *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x0028))
#define CPU_GIC_GICC_APR0               *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x00D0))
#define CPU_GIC_GICC_NSAPR0             *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x00E0))
#define CPU_GIC_GICC_IIDR               *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x00FC))
#define CPU_GIC_GICC_DIR                *((volatile uint32_t *)(CPU_GIC_CPU_INTERCACE + 0x1000))

#define CPU_GIC_GICH_HCR                *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x000))
#define CPU_GIC_GICH_VTR                *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x004))
#define CPU_GIC_GICH_VMCR               *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x008))
#define CPU_GIC_GICH_MISR               *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x010))
#define CPU_GIC_GICH_EISR0              *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x020))
#define CPU_GIC_GICH_EISR1              *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x024))
#define CPU_GIC_GICH_ELSR0              *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x030))
#define CPU_GIC_GICH_ELSR1              *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x034))
#define CPU_GIC_GICH_APR                *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x0F0))
#define CPU_GIC_GICH_LR0                *((volatile uint32_t *)(CPU_GIC_VIR_INTF_CTL + 0x100))
#define CPU_GIC_GICH_LR0_ADDR                                  (CPU_GIC_VIR_INTF_CTL + 0x100)

#define CPU_GIC_GICV_CTLR               *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0000))
#define CPU_GIC_GICV_PMR                *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0004))
#define CPU_GIC_GICV_BPR                *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0008))
#define CPU_GIC_GICV_IAR                *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x000C))
#define CPU_GIC_GICV_EOIR               *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0010))
#define CPU_GIC_GICV_RPR                *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0014))
#define CPU_GIC_GICV_HPPIR              *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0018))
#define CPU_GIC_GICV_ABPR               *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x001C))
#define CPU_GIC_GICV_AIAR               *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0020))
#define CPU_GIC_GICV_AEOIR              *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0024))
#define CPU_GIC_GICV_AHPPIR             *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x0028))
#define CPU_GIC_GICV_APR0               *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x00D0))
#define CPU_GIC_GICV_NSAPR0             *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x00E0))
#define CPU_GIC_GICV_IIDR               *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x00FC))
#define CPU_GIC_GICV_DIR                *((volatile uint32_t *)(CPU_GIC_VIR_CPU_INTF + 0x1000))

/*=================================================================================================
*                                STRUCTURES AND OTHER TYPEDEFS
=================================================================================================*/


/*=================================================================================================
*                                GLOBAL VARIABLE DECLARATIONS
=================================================================================================*/


/*=================================================================================================
*                                     FUNCTION PROTOTYPES
=================================================================================================*/
#ifdef __cplusplus
}
#endif

#endif /* PORT_H */

/** @} */
